Moore’s Law has slowed down, but progress continues in logic development as a new roadmap points to sub-1nm process nodes around 2034.
It will Be Years Before Process Technology Go Sub-1nm, But They Are In Development: 0.7nm by 2034 & <0.2nm by 2046
Process technologies have slowed down as we transition into the Angstrom era. While newer nodes continue to offer uplifts, they are getting expensive to produce as the machinery needed to achieve newer designs comes at higher costs. Furthermore, the reliance on chiplets through advanced package solutions has reduced the need to shift to newer nodes immediately, as the former provides a scalable and cost-effective chip design.
IMEC, the world’s largest independent research and innovation center for nanoelectronics, based primarily in Belgium, has shared its roadmap through the 2020s-2040s, highlighting the major process innovations that are expected in the semiconductor industry.
Moore’s Law Continues To Live On, But At A Slower Pace
The first roadmap highlights the Logic scaling from 1998 to 2026. From 1998 to 2010, logic density was scaling at 50% each year. This means that the area of SRAM was being halved every year, but since 2010 till 2026, we are now approaching linear scaling. This means that no significant scaling has been achieved in logic over the past few years.
But the industry itself demands more performance, and that comes through higher densities. That is where 2.5D/3D technology has shown its prowess, but there are limitations to that, too, in terms of power, temperatures, and costs. Recently, TSMC has put out its SoW (System-on-Wafer) packaging technology, which scales up the existing CoWoS (Chip-on-Wafer-on-Substrate) design, for massive compute-oriented chip designs. AI chip designs also require close coordination between the chip & memory, too, with DRAM playing an essential role in powering today’s Agentic AI needs.
But despite the reliance on chiplets and advanced packaging solutions increasing tenfold, the logic technologies will continue to evolve in the future. To highlight some of the imminent technologies, IMEC has presented its latest “Logic Device Roadmap”. The roadmap is more research-oriented and gives us a timeframe for when to expect next-gen process technologies. The year respective to the process node does not indicate a production timeframe, but links to the development completion of the technology.
The Sub-2nm Era
Looking at the roadmap, we first have the “Nanosheet” nodes, which will use Nanosheet FETs or GAA (Gate-All-Around) transistor technology. Nanosheets will start with TSMC’s N2, which rolls out this year. The process technology is already in mass production with the follow-up nodes, sub-2nm, going into production readiness state by the end of this year. TSMC and Intel plan on launching several sub-2nm technologies, including A16, A14, A13, A12 from TSMC, and 14A, along with its optimizations from Intel.
The last Nanosheet-based node is expected to be A10 around 2031, which will lead us into the sub-1nm era.
The Sub-1nm Era
For sub-1 nm process technologies, semiconductor manufacturers are expected to utilize Complementary FETs or CFETs, which take the same nanosheet technology and stack them vertically. This leads to reduced cell area and a transistor density boost. The first process node featuring CFETs is expected by 2034 and is going to offer the first sub-1 nm process tech.
The A7 (0.7nm) process technology will be followed by A5 (0.5nm) by 2036, and A3 (0.3nm) by 2040. As the CFET technology improves, we can see the transistor density of CMOS logic circuits increase by up to 80%.
Next, we will transition to the 2 Angstrom era, which will feature 2D FET technology. This is where the use of new materials will come into play to form either 2D CFETs or 2D Nanosheet structures. 2D FETs will see their first application by 2043 in an A2 (0.2nm) node, and will be followed by sub-A2 (<0.2nm) technology by 2046. Once again, the roadmap is theoretical; a lot can change in the development cycle & timeframe for each respective technology.
The next roadmap highlights the BEOL (Back-End-of-Line) scaling, which showcases the materials used to connect transistors. The current standard approach is Dual-Damascene & Single-Damascene, which involves copper process with a metal pitch of 24-26nm. This process will improve till 2028 and the A14 technology, seeing a reduction of pitch size to 20-22nm.
As technology evolves, 1nm and sub-1nm class nodes will transition into Semi-damascene / Subtractive Metallization approaches. Here, Ru (Ruthenium) will replace copper, forming intentional air gaps and self-aligned vias. These offer barrierless vias for reduced resistance, and less “wasted” volume for higher logic conductivity.
The next major step will be for 0.5 and sub-node technologies, which will leverage alternate materials such as Epitaxial PtCoO₂ (platinum cobalt oxide) on Sapphire, which offer exceptionally lower resistance. These will lead to ultra-low pitch sizes ranging from 16nm down to 12nm,
| Year | Node | Metal Pitch (MP) | Process Type | Key Innovation Highlighted |
|---|---|---|---|---|
| 2025 | 2 nm | 24–26 nm | Dual-Damascene & Single-Damascene | Barrierless vias (Cu, W, Mo) |
| 2028 | A14 | 20–22 nm | Dual-Damascene & Single-Damascene | — |
| 2031 | A10 | 18–20 nm | Transition → Semi-damascene | Ru with air gaps + self-aligned vias |
| 2034 | A7 | 16–18 nm | Semi-damascene (Subtractive) | Ru with air gaps + self-aligned vias |
| 2037 | A5 / A3 | 12–16 nm | Semi-damascene (Subtractive) | Alternate metals (e.g., epitaxial PtCoO₂) |
Moving gears to power technology, the roadmap covers upcoming features till 2032. The plan mainly involves moving the IVR (Integrated Voltage Regulators), currently featured on the mainboard PCB, to inside the PCB itself. These new IVRs will also help reduce voltages from 48V DC to 12V DC, and then further down to just 0.8V DC.
The 2026-2027 roadmap shows IVR within the PCB of the mainboard itself. The IVR sits right below the main chip package, which houses the interposer that is allocated to various 3D ICs and DRAM packages. These solutions will be integrated within the package itself by 2028-2032, leveraging next-gen tech such as 2.5D MIM capacitors and Can/SI Power devices. Remember that MiM (Metal-in-Metal) capacitors are also being leveraged by Intel’s EMIB for 2.5D advanced packaging solutions. EMIB–T also embeds power to logic via TSVs (Through Silicon Vias).
These roadmaps go on to show that despite physical limits in traditional scaling, 3D stacking, new materials, and smart architecture will drive higher density, better performance, and efficiency for decades. This roadmap underscores strong progress in chips powering AI, HPC, and future tech.
| Year | Node | Architecture / Transition | Key Features & Innovations | Technical Specifications (BEOL Wiring & Materials) | Context / Notes |
|---|---|---|---|---|---|
| 2018 | N7 (7 nm) | FinFET | First mass-produced FinFET node in the roadmap; baseline for logic scaling | SRAM cell area: 0.025–0.023 μm² | Ongoing logic improvements |
| 2020 | N5 (5 nm) | FinFET | Continued FinFET scaling; major density & performance boost for AI/HPC | Density/performance enhancements | AI & high-performance computing focus |
| 2023 | N3 (3 nm) | FinFET | Final FinFET node; SRAM cell area stability maintained despite halted horizontal scaling | SRAM cell area stability | Start of the 3D vertical scaling era |
| 2025 | N2 (2 nm) | Nanosheet FETs (GAA) | First transition from FinFET to Gate-All-Around nanosheet transistors | BEOL min. pitch: 24–26 nm (Cu wiring, dual/single damascene) | Start of 3D vertical scaling era |
| 2028 | A14 (1.4 nm / 14 Å) | Improved Nanosheet FETs (GAA) | Further nanosheet optimization for higher transistor density | BEOL min. pitch: 20–22 nm | Continued vertical scaling |
| 2031 | A10 (1.0 nm / 10 Å) | Continued Nanosheet FETs | Introduction of advanced wiring materials & techniques to combat power & heat issues | BEOL min. pitch: 18–20 nm; Ru (ruthenium) wiring, air gaps, subtractive manufacturing, self-aligned vias | Addresses rising power consumption |
| 2034 | A7 (0.7 nm / 7 Å) | CFETs (Complementary FETs) | Major innovation: Vertically stacked p-channel + n-channel nanosheet FETs; 1.6–1.8× density gain over nanosheet | BEOL min. pitch: 16–18 nm (Ru + air gaps + self-aligned vias) | First CFET node; solves CMOS logic density limits |
| 2037 | A5 (0.5 nm / 5 Å) | Continued CFETs | Coordinated FEOL/BEOL optimizations for HPC; focus on power & thermal management | BEOL min. pitch: 12–16 nm (R&D stage) | HPC & AI performance push |
| 2040 | A3 (0.3 nm / 3 Å) | Continued CFETs | Higher integration level; continued 3D scaling | Builds on A5 BEOL improvements | Long-term density scaling |
| 2043 | A2 (0.2 nm / 2 Å) | 2D FETs (first disclosure) | Breakthrough: Replacement of nanosheet channels with 2D materials; ultra-high density | End of the traditional FinFET era | First-time public disclosure of 0.2 nm node |
| 2046 | Extends the CFET architecture with 2D channel materials | Continued 2D FETs | Ultimate miniaturization; maximum transistor density via 2D materials | Maximized density through 2D materials & 3D interconnection | Roadmap endpoint; beyond-2040s vision |
News Source: 36kr
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech’s Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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